Ziptronix developed a method to enable silicon, III-V and other substrates to be bonded in a 3D fashion, to maximize the density of signal paths that chips use to interconnect transistors. With DBI® technology, Supercontacts (SC) are used to vertically route interconnect between chips with dramatically reduced drive and ESD requirements. This capability enables an ultra-high density vertical interconnect between transistors, gates, and/or devices required to build scalable 3D ICs. This methodology enables compelling cost and performance factors to drive mainstream adoption of three-dimensional integrated circuits (3D ICs).

The industry faces significant design and cost barriers as two-dimensional devices migrate to process nodes below 90 nanometers (nm). It is increasingly difficult to scale technology in two-dimensional devices, as is evident by the increasing dominance of interconnect delay in limiting System-on-Chip (SoC) bandwidth and increasing difficulty in yielding mixed-signal ICs. DBI® technology extends scalability to these nodes by alleviating the interconnect delays with scalable 3D routing and allowing design partitioning in 3D..

DBI® further obsoletes inefficient through-die vias used in previous 3D IC integration methods that disrupt BEOL interconnect routing, consume excessive silicon, and hinder qualification. This technology provides the industry's highest density of electrical connections for 3D ICs bonded in die-to-wafer or wafer-to-wafer scale methodology without requiring the etching and filling of vias through BEOL interconnect.

"DBI® can achieve over 100,000,000 electrical connections per square centimeter; a significant increase over the ~ 100,000 connections per square centimeter density achieved with through-die vias used in other 3D interconnect approaches."

Competing 3D processes require large area exclusions that require valuable die area and result in the disruption of the BEOL interconnect stack of at least one IC layer in a 3D IC. DBI® allows for direct connections to be made between ICs as part of the bond process without disrupting and compromising the interconnect stack. With DBI®, 3D IC cost is minimized by avoiding design exclusions in the interconnect stack and delivering a vertical interconnections between IC layers in a 3D IC that scale with the process nodes.

DBI® is an evolution of the Ziptronix ZiBond™; direct bond technology that enables covalent, room temperature bonds between silicon oxide surfaces of each chip in the 3D structure. This breakthrough technology utilizes a chemo-mechanical polish to expose metal patterns embedded in the silicon oxide surface of each chip. When the silicon oxide and metal connection points of each chip are aligned and bonded using the company's ZiBond™; room temperature direct oxide bonding technology, the alignment is preserved, as opposed to other bonding techniques that require heat and/or pressure as part of the bonding process resulting in potential misalignment. The oxide bonding is characterized by a very high bond energy between the surfaces, which brings the metal contact points close to each other to form effective electrical connections between chips. The low resistance of these electrical connections enables better power efficiency and reduces the overall power consumption of the 3D IC.