Ziptronix’s 3D Integration process bonds various substrates (Si, InP, GaN, SiGe, GaAs, or passive materials) at the die and wafer level or at the wafer to wafer level forming a single chip.  We are now able to optimize connections between semiconductor chips by eliminating wire bonding, solder bumping, expensive system-on-chip or large flip-chip techniques. The 3D IC process ergonomically layers chips to enable high volume manufacturing of vertically integrated circuits, and to achieve an optimized, scalable and much less costly process.

Major benefits of Ziptronix’ 3D integration process are:

• Large designs can be partitioned into smaller, less expensive devices without degrading performance
• Short vertical interconnects replace long, cross-chip interconnects, and enable higher operating frequencies
• I/O drivers required to power off-chip signal lines are minimized
• ESD protection requirements are minimized further reducing power requirements
• Dissimilar semiconductor materials can be bonded together to enable integration never before possible
• "Late stage bonding" allows integration of best-in-class devices tailored to meet specific customer needs
• Device thinning after bonding enables the thinnest device stacks of any 3D technology
• Wafer-scale fabrication after bonding allows for a greater diversity of 3D structures
• High post-bond temperature capability allows post-bond defect annealing
• Superior reliability due to elimination of solders and alloys
• Ziptronix' die-to-wafer bonding process allows known-good-die selection to be performed prior to bonding, eliminating yield loss associated with wafer-bonding
• Existing devices can be readily combined, eliminating the difficult process of licensing and integrating soft IP, drastically shortening time to market
• Existing fabrication facilities are employed in new ways without additional investment

Ziptronix technology enables system architects to design in three dimensions, eliminating multiple packages, minimizing signal paths and reducing the need for power-hungry drivers to boost signals off chip. Logic, memory and analog devices can be fabricated in their respective optimum processes, and can then be assembled as an integrated SoC. Ziptronix 3D integration technology delivers continuation of Moore’s Law with simultaneous improvements in size, cost, speed and power consumption.

More Info on 3D Integration

3D Integration for Mixed Signal Applications

Benefits of 3D Integration in Digital Imaging Applications