Future Wafer Level Packaging (WLP) Solutions for CMOS Image Sensors

Contributor: Ziptronix, Inc.

April 2009 - Ziptronix – Morrisville, N.C.
With the 2007/2008 announcements of Toshiba, Aptina (Micron), Oki/Zycube, ST Micro and Samsung, WLP using backside TSV has become the packaging method of choice for today’s CMOS Image sensors (CIS) [1]. After vias are etched from the wafer backside  to the back side of the Al pads, subsequent insulation, redistribution and bumping is reminiscent of today’s WLP technologies. This is shown in Figure 1. Based on it’s acceptance in the market place, it is clear that such technology results in the smallest currently possible device at acceptable  consumer electronics pricing.

Fig 1. WLP for CMOS Image Sensors [ref: ST Micro]

 Manufacturers roadmaps indicate that we can expect the following  technology trends moving  forward: (1) a conversion to backside illumination technology (BSI) ; (2) 3D bonding of partitioned circuitry.

The move to Backside Illumination

Instead of illuminating a CMOS image sensor from the top side (front) of the die, backside illumination (BSI) collects photons from the backside so the light enters the device unobstructed  by the metal and dielectric layers of the interconnect structure as shown in the Fig 2.This technology involves thinning the backside of the wafer close to the photodiode level and placing the color filter and lenses on this wafer backside.  When compared to FSI, BSI architecture delivers reduced pixel size, increased sensitivity per unit area, improved quantum efficiency and reduced cross talk which lead to significant improvements in image quality and reduction in cost. Since light directly strikes the silicon, BSI can deliver superior low-light sensitivity and allows for shorter lens heights which in turn allows for thinner camera modules.  

                                     A                                                 B

Fig. 2   Frontside Illumination (A)  vs   Backside Illumination (B) [ref: Sony]

3D Stacking and Bonding with TSV

The next generation of product is expected to require redesign the CIS die.  Bonding  circuitry such as A/D,  read-out IC (ROIC) and/or digital signal processor, in separate strata (layers) to he CIS die will form true, stacked, 3D integrated structures. Stacking the sensor with the other circuits, required to process the image data, will result in smaller volume, lower weight products with better resolution and faster response. Such a Zycube design is shown in Figure 3 where A/D converter circuitry is bonded directly to the BSI CMOS Image sensor using TSV.

Figure 3. BSI CIS 3D stacked  with A/D converter [ref: Zycube ]

In order to achieve such evolution in CMOS CIS, low cost of ownership (COO) bonding solutions must be available. 

Ziptronix low  temperature oxide bonding technology, Zibond™ [2] and low temperature metal-metal bonding technology , DBI® [3] , are positioned to take a
prominent role in the adoption of both of these technology options.

BSI by Direct Oxide Bonding

BSI technology does not require TSV but does require solutions for handling thinned wafers. A preferred solution is to direct oxide bond the sensor wafer front surface to another oxide coated wafer which can then serve as a permanent “handle wafer” for thinning the backside.

Direct oxide bonding processes require extremely smooth (< 0.5 nm RMS) and clean surfaces which are readily achieved with standard CMP. When such SiO2 surfaces are placed into contact, they initially form relatively weak “van-der-Waals” bonds. Subsequent heating to elevated temperatures is necessary to achieve high bond strength through the formation of covalent Si-O-Si bonds according to Eq. 1.

Si-OH + Si-OH ---------- Si-O-Si + H2O         Eq (1)

The high thermal budget required for this condensation reaction to proceed  is not suitable for bonding IC, however, modifying the surface chemistry allows the formation of chemical bonds at significantly lower temperatures. Such surface modification technology has been reported [ 4,] and patented [5], and is referred to as Zibond™.

One example of  Zibond™ simply requires a plasma treatment followed by an aqueous ammonium hydroxide rinse (Figure 4). By such surface treatments bond energies in excess of 1 J/m2 can be obtained [6].

Figure 4 Ziptronix Zibond™ Direct Oxide Bonding

3D stacking and TSV Metal – Metal Bonding with DBI®

Recent reports indicate that oxide bonding currently has 35% better placement accuracy and that oxide bonding provides a 10-20X better throughput  than Cu-Cu thermocompression bonding as shown in Table 1 [7].

Table 1  Comparison of 3D Bonding Processes [7]

DBI® - the Direct Oxide Bond  / Metal – Metal Bond  Hybrid Approach

Direct Bond Interconnect (DBI®) is a hybrid of direct oxide bond technology and metal-metal bond technology in that vertical electrical interconnections are made integral to the SIO2  bond process [8-10].  Vertical interconnections in  DBI® are achieved by preparing a heterogeneous surface of non-conductive oxide (SiO2) and conductive metal.  After ZiBond™ activation and termination of the SiO2 surfaces, the co-planar metal / SiO2 surfaces can be direct bonded at room temperature. Bonding initially takes place on the activated SiO2 surfaces. Alignment tolerances less than +/- one micron over three standard deviations are possible with commercial pick-and-place tools.

The oxide / metal interfaces can be fabricated in two ways. In method (1) a silicon dioxide layer is deposited on the face of the wafer, vias are then etched and filled to connect to the conductive BEOL contact underneath. The via(s) can be filled with DBI metals such as Cu, W, Au or Ni as is detailed in ref 8. This is followed by planarizing the surface to an acceptable RMS and flatness by CMP. This method is analogous to the tungsten and copper damascene processes used in aluminum and copper based CMOS BEOL, today. For backside preparation the same sequence is followed after thinning to expose the bottom of the TSV.

In method (2) the DBI® metal structure(s) is prepared on a surface ( via) or backside (TSV) metal, then oxide is deposited, followed by CMP to expose the metal / SiO2 coplanar surface. This method is also a single mask level process if the seed layer used for electroplating is blanket etched following electroplating.  As with the Damascene Metal Fill method, these unit process steps are also similar to those used in volume foundry interconnect stack fabrication manufacturing.

This second method is depicted in Figure 5 using Ni as the DBI® metal . Ni is a unique DBI metal since its hardness allows an easy CMP process to generate the required coplanar surface.  In the case of copper, special CMP techniques must be used to eliminate the dishing that normally occurs in the soft copper metal in the presence of the hard oxide during CMP. To use Cu special CMP techniques must be used.

Subsequent heating at 300 °C in a standard clean room oven can facilitate formation of a low resistance Ni-Ni interface. The combination of a low capex pick-and-place tool and high wafer throughput lead to lower COO for the entire process.

Figure 5 Ziptronix Direct Bond Interconnect Process

Conclusions:

CMOS Image sensor technology is evolving rapidly as handset and camera requirements for smaller device size and higher device resolution continue. It is expected that backside illumination technology will become generally accepted in the near future. It is also expected that 3D IC integration will be used to stack CIS driver and signal conversion circuitry in order to achieve future handset requirements. The Zibond™ and DBI® technologies offered by Ziptronix are low COO pathways for implementing these changes.

References:

[1] P. Garrou, “3D Commercial Activity” in Handbook of 3D Integration , P. Garrou, C. Bower, P. Ramm Eds., Wiley-VCH, 2008, p. 273 ; P. Garrou, “on Mechanical Bulls, Rollercoasters and CIS with TSV “,in Perspectives From the Leading Edge, Semicondiuctor International online ( www.semiconductor.net) blog, 09/22/2008  
[2] P. Enquist, “High Density Direct Bond Interconnect  Technology for 3D Integrated   Circuit Applications”, Mat. Res. Soc. Symp. Proceed., Vol 970, 2007, p. 13
[3] P. Enquist, “3D Integration at Ziptronix”, chapter 25 in Handbook of 3D IC Integration: Technology and Applications, P. Garrou, C. Bower and P. Ramm Eds., Wiley VCH, 2008.
[4] Q. Y. Tong, “Room Temperature Metal Direct Bonding”, Applied Physics Letters, 89,   1 (2006).
[5] USP 6,902,987, June 7, 2005.
[6 P. Enquist, “Room Temperature Direct Wafer Bonding for Three Dimensional Integrated Sensors”, Sensors and Materials, Vol. 17, No. 6 (2005), p. 307.
[7]  T. Matthias, ”Enabling Technologies for 3D Integration”, 3D Architectures for Semiconductor Integration and Packaging, Burlingame CA, 2008.
[8]  USP 6,962,835 
[9] P. Enquist, “3D Integration at Ziptronix”, in. Handbook of 3D Integration, P. Garrou, C. Bower, P. Ramm, Eds., Wiley-VCH, 2008