Staying On the Path to Moore’s Law Requires 3D Integration  

Contributor: Ziptronix, Inc.

August 19, 2009 -- As the semiconductor industry struggles to maintain its momentum down the path of Moore’s Law, it is becoming clear that in addition to scaling line widths and chip sizes downward, some form of 3D IC integration will be necessary to achieve the interconnection density, manufacturing yields and cost targets. Even as device physicists continue to debate whether the physical limits of 2D scaling will be reached at the 22-nm node or somewhere beyond, the rest of the industry is recognizing the increasing practical and financial constraints being imposed by each new milestone on the technology roadmap.
By vertically stacking and interconnecting semiconductor layers (3D integration), as opposed to continuing to shrink line widths, chip designers have the potential to get around the limitations of geometric scaling; enable a significant increase in performance and reduction in power consumption through reduced signal paths; and achieve true cost reduction through the use of proven fabrication techniques that will increase yields.
The crucial processing technology elements for 3D IC integration include: 1) through silicon via (TSV) formation; 2) wafer thinning; and 3) scalable wafer-level bonding technologies with 3D interconnect for W2W (wafer-to-wafer) or D2W (die-to-wafer) fabrication processes. The semiconductor manufacturers who adopt the optimum combination of these technologies will be the ones who lead the industry to the next level of higher device performance and lower fabrication costs.
TSV formation sequence strategies
Through-silicon vias (TSVs) can be formed "first" (during IC fabrication), either during FEOL (front end of line) processes, using highly resistive polysilicon material to fill the vias; or before BEOL (back end of line) processes prior to chip interconnect, using a conductive metal such as copper (Cu), tungsten (W), or nickel (Ni) for via fill material. These TSVs are very scalable because they are only built a few microns into the silicon substrate and do not impede the conventional BEOL routing. These TSVs can be bonded "as is" after suitable thinning to reveal the TSVs, or a conductor like nickel (Ni), copper (Cu) or other suitable material may be patterned on the revealed TSV and planarized with oxide deposition and CMP in preparation for bonding.
Conversely, TSVs can be formed "last" (after the IC processing is completed) by etching through to expose conventional BEOL metal through the backside of the wafer.
TSV-first processing is typically implemented at an IDM or semiconductor foundry during wafer fabrication, while TSV-last processing can be implemented at either a foundry or by an outsourced semiconductor assembly and test (OSAT) facility.
Wafer thinning options
Wafer thinning is typically accomplished by mechanical grinding of the wafer’s back surface, silicon CMP, and dry etching (e.g., sulfur hexafluoride), or wet etching (e.g., potassium hydroxide or tetramethyl ammonium hydroxide). An important consideration when performing CMP processes on silicon wafers with embedded metal "plugs" (the exposed surfaces of TSVs) is that typically the metal, especially copper (Cu), is softer and more ductile than the surrounding silicon and can result in "dishing" or a non-planar surface, which can complicate the bonding process.
Wafer-level bonding with interconnect technologies
Currently available wafer-level bonding technologies include: 1) conductive adhesives, 2) metal-to-metal thermocompression (typically a Cu-to-Cu bonding process); and 3) direct insulative bonding with embedded conductive 3D interconnect, which relies on natural molecular forces to provide surface attraction between two levels of wafers prepared with an insulator like silicon dioxide.
Metal-to-metal thermocompression bonding has been the preferred technology for 3D IC integration, primarily because it forms both mechanical and electrical interconnections simultaneously. However, achieving the conditions necessary for proper bonding requires extremely high temperatures (350° to 400°C), in addition to a minimum of 30 minutes under pressure, which affects both alignment accuracy as well as throughput; both of which have a direct impact on processing costs.
While both conductive adhesives and Cu-Cu thermocompression technologies are commercially available at wafer foundries and OSAT vendors, they both have issues of alignment accuracy, as well as throughput delays. According to a recent comparison of 3D IC bonding processes supplied by wafer processing equipment maker EVG, both Cu-Cu thermocompression and polymer adhesive technologies suffer from a limited bonding accuracy (~1.8µm) at their current development levels, with a projected enhancement to ~1.2µm with future developments.
Further, both of these processes require extensive processing time in specialized chambers designed to achieve the necessary conditions for proper bonding. It is estimated that Cu-Cu compression technology requires about an hour of processing time per wafer, and up to four process chambers per throughput balanced tool, which results in typical throughput of about four wafers/ hour/ tool. Polymer adhesives require up to 30 to 60 minutes per wafer, with up to four process chambers, with a throughput capacity of four to eight wafers/ hour/ chamber.

Direct oxide (molecular) bonding, by contrast, currently has a significant advantage in bonding alignment accuracy (~1.3µm), with projected improvement to less than 0.5µm in future iterations of the technology. More importantly, this technology requires only three to six minutes per wafer in a single process chamber, which can accommodate as many as 10 to 20 wafers/ hour/ chamber.
The reduced processing time and increased alignment accuracy translates to higher throughput and lower costs. According to a recent study by Yolé Development, an independent semiconductor research analyst firm, direct oxide bonding was the lowest-cost bonding technique when compared to Cu-CuTC (copper-to-copper thermal compression) or adhesive technology. In its revised study results, Yolé concluded that for a typical fab running 500,000 300-mm wafers per year using 1 x 20µ vias, the bonding costs per wafer level (including CMP) were: $57 for Cu-Cu; $22 for adhesive; and just $12 for direct oxide bonding technology.

Figure 1. Yolé Development bonding cost study results.

As a consequence, the optimal solution for large scale, profitable 3D IC integration with high yields and high throughput will require direct oxide bonding technology that incorporates conductive or metal-to-metal bonding while eliminating the high temperature and pressure required for conventional Cu-CuTC processes. Such a technology has been developed by Ziptronix under the name Direct Bond Interconnect, or DBI®.
Direct Bond Interconnect technology includes the direct oxide bonding process and conductive or metal-to-metal interconnection technology by achieving vertical interconnections through preparation of non-conductive heterogeneous oxide (SiO2) and conductive materials or metal. By activating and terminating the planarized surface of the wafer, for example with a nitrogen plasma, the formation of chemical/ molecular bonds is enabled at significantly lower temperatures, thus eliminating the high temperature and pressure of Cu-CuTC processes.
To achieve 3D IC stacking, planarized DBI interfaces are prepared on both the top and bottom of the wafers, with interconnections to TSVs as desired. As part of the CMOS last metal layer deposition, a Cu, Ni, or other suitable connection to the BEOL-processed interconnect underneath is made. This may include industry standard silicon oxide deposition, via cut, metal deposition, and CMP unit processes. The topside contacts are then bonded to the backside, which has been thinned to expose the bottom of the next layer TSVs or topside of the next level wafer.
Alternatively, a heterogeneous DBI® surface can be prepared by seeding a metal layer on top of a TSV structure, then depositing an oxide layer. Nickel is often used for this DBI metal layer, since its hardness facilitates easy CMP processes. Copper can also be used with suitable adjustments to the CMP to mitigate "dishing" that can otherwise occur as the softer copper undergoes CMP. When the surface is flattened through CMP processing to expose the TSV metal and SiO2 coplanar surface, the room temperature bonding process can occur.

Figure 2. Ziptronix DBI process flow diagram.

The bonded structures may be heated to facilitate 3D interconnections. The optimum temperature depends on the DBI® metal used. For example, Ni DBI may be heated to ~300°C while Cu DBI may be heated to only ~150°C to form monolithic low-resistance metal-to-metal interfaces. The activated and terminated oxide layers are bonded together with sufficient bond energy to generate internal pressure when the DBI metal expands with the increase in temperature to form a reliable metallic bond to complete the interconnection. It is also possible to form direct metal-to-metal interconnections without any heating depending on the type of DBI metal and planarization.
These processes are similar to currently-existing volume foundry manufacturing steps, and can thus be easily implemented at the wafer foundry level with minimal capital equipment expense.
Another advantage of the DBI® process is that it can be employed on wafer-scale level (wafer-to-wafer), or as a D2W (die-to-wafer) processing step. In D2W processes, the base wafer is prepared and then the die wafer is singulated, tested and placed on top of the base wafer using standard pick-and-place tools. This D2W process could be readily implemented at a commercial foundry or OSAT vendor facility with suitable particle control.
In summary
As semiconductor manufacturers continue to seek new paths to design and fabricate denser ICs to keep pace with Moore’s Law, 3D IC integration will become an enabling technology in the development of the next generation of semiconductors. Direct oxide bonding is beginning to emerge as the technology of choice to achieve 3D integration because of its lower total cost of ownership, and its ability to be implemented across all levels of the semiconductor supply chain – IDMs, commercial wafer foundries, and OSATs.