Products |
| 3D Integrated Circuits |
| 3D integration of a CMOS PROM with merchant CMOS logic (JPEG - 112K) |
| Focused ion beam micrograph cross-section of an Indium Phosphide epitaxial stack bonded to within 4.5 microns of merchant CMOS logic (JPEG - 33K) |
This picture shows the die to wafer bonding in action where we take the donor die, place it in a waffle pack and then bond it to a host wafer. This is using a standard pick and place machine and because the bond remains active for hours, we can run several lots through at a time.
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This is a close up picture of a 3DIC; specifically a set of memory die bonded to a logic wafer. The memory die are bonded face down to the logic wafer face up. The die is subsequently thinned to about 10 microns. Electrical contact between the memory & logic is made by a via etch to the memory & logic bond pads followed by an interconnect metalization over the memory die edge.
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This picture demonstrates the ability to do a "known good die select" and bond those die using the ZiROC® technology directly to a target wafer ensuring that yields remain high.
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| Engineered Substrates |
| Engineered Substrate (JPEG - 710K) |
LiN to Silicon
From left to right, a single wafer of Silicon, a single wafer of Lithium Tantalate, a bonded wafer pair of Lithium Tantalate to Silicon using ZiROC® technology. |
LiTaO3 to Quartz
From left to right, a single wafer of Quartz, a single wafer of Lithium Tantalate, a bonded wafer pair of Lithium Tantalate to Quartz using ZiROC® technology. |
Engineered Substrate Family
Various types of semiconductor materials can be bonded together to form Engineered Substrates |
Bonded wafer Pair
Lithium Tantalate is bonded to Quartz to produce a custom engineered substrate. |
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| Wafer Scale Encapsulation |
Glass caps are hermetically bonded to allow optical access to the device cavity. The covalent ZiROC® bond withstands post fabrication processing such as wafer sawing and final packaging steps.
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Cross sectional view of a MEMs device which was packaged at wafer scale and then sawed into individual die. This device is consists of a 4 wafer "sandwich" where the inside cavity was etched out and then a glass cap was bonded to the wafer using the ZiROC® technology.
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Hermetic, wafer-scale caps are bonded directly to the MEMS and RF device wafers in the Ziptronix facility. Room-temperature bonding eliminates residual thermal stress between materials with different coefficients of thermal expansion. ZiROC® eliminates mechanical dislocations which frequently occur with heating and cooling cycles typically found in thermal fusion bonding methods.
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Single or multiple layers of material can be bonded to form custom cavity geometries for MEMS or RF devices. The ZiROC® surface activation chemistry is compatible with MEMS technologies eliminating contamination failures caused in back-end processing operations.
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