ECONOMICAL LOW TEMPERATURE
WAFER/DIE BONDING PROCESS IDENTIFIED AS
MISSING LINK IN EMERGING 3D IC SUPPLY CHAIN
Ziptronix CEO Dan Donabedian to highlight 3D IC developments at conference…
November 11, 2008
Burlingame, Ca. – As the semiconductor industry strives to find new technologies to enable continued scaling, lower wafer processing costs and increased functionality of next generation ICs, 3D CMOS integration is poised to become a mainstream semiconductor technology, according to Ziptronix CEO Dan Donabedian. At an upcoming technical conference, Donabedian will highlight his company’s patented Direct Bond Interconnect (DBI®) technology, and the enabling role it will play in the emerging 3D IC supply chain.
Ziptronix, Inc., based in Research Triangle Park, NC, is a leader in IP for innovative 3D integration technology for advanced CMOS ICs, with established patent protection for its ZiBond™ low temperature covalent bonding (US Patent 7,387,944) and DBI® direct bond interconnect (US Patent 6,962,835) technologies.
Donabedian will speak at the fifth annual 3-D Architectures for Semiconductor Integration and Packaging conference, scheduled for November 17 – 19, 2008 in Burlingame, CA. His presentation will address the recent developments in the 3D IC supply chain, and the “missing link” of a reliable, economical, high throughput low temperature oxide bonding process that achieves a metal connection without requiring high temperature thermal compression.
“Because our DBI® and ZiBond™ processes can be implemented at all levels of the supply chain – by the OEMs/IDMs; by fabless and ‘fab-lite’ companies; by the major foundries; by semiconductor tool manufacturers and EDA vendors; and by the OSAT houses – Ziptronix is now in a position to enable true 3D integration to become a mainstream semiconductor technology,” Donabedian explained. “We anticipate being able to add value to each phase of this emerging 3D IC supply chain through the licensing and adoption of this patented technology,” he continued.
Ziptronix technology
Ziptronix technology employs nickel as a DBI® metal to reliably interconnect to copper, tungsten, aluminum TSVs or other interconnect levels, while providing adequate planarity of the oxide/metal interface for a strong, reliable bond on either backside or frontside interconnects. It also resolves the problem of surface depression (dishing) that typically occurs with CMP and copper. Patented ZiBond™ technology chemically modifies the surface oxide, enabling the formation of a strong, reliable oxide bond at room temperature.
Lower cost bonding with interconnect is achieved by eliminating the need for compression of the bonded wafers during the interconnect phase. Bonded wafers can be batch-processed at ~300°C without compression to complete both the electrical connection and form a reliable metallic bond at the Ni-to-Ni interface. Bonding can be accomplished using standard pick-and-place tools, thus requiring minimal capital expenditure.
The Ziptronix DBI® process can be implemented for face-to-face or back-to-face configurations in wafer-to-wafer or chip-to-wafer formats to achieve high density 3D interconnects (up to 108/cm2) and is scalable to sub 1-micron pitch with improved alignment and placement tools. Ziptronix has demonstrated 3-micron and 1.5-micron pitch interconnects using existing alignment tools.
Lowest cost bonding technology available
In a recent study by Yolé Development, an independent semiconductor research analyst firm, the Ziptronix DBI® process was identified as the lowest cost bonding technique ($12/wafer bonding level) when compared to Cu-CuTC copper-to-copper thermal compression ($57) and adhesive technologies ($22).
For more information about Ziptronix 3D IC technology, contact info@ziptronix.com, call 919-459-2400.
About Ziptronix
Ziptronix is a pioneer in the development of low temperature oxide bonding technology for advanced semiconductor applications. Founded in October 2000, Ziptronix was spun out from North Carolina’s RTI International for the purpose of commercializing their revolutionary wafer and die bonding (ZiBond™) and interconnect (DBI®) technologies. The company has an extensive worldwide patent portfolio covering the fundamental concepts behind economical low temperature oxide bonding.
Ziptronix technology provides the lowest cost solution for low temperature wafer-to-wafer and die-to-wafer bonding, delivering significant advantages in size reduction, lower production costs, lower power consumption and increased system performance.
Ziptronix licenses its technology to customers across the entire semiconductor manufacturing supply chain – OEMs/IDMs, foundries, semiconductor equipment manufacturers and OSATs – to enable them to quickly implement reliable, economical 3D IC integration using standard processing equipment.
About the conference
The 5th annual 3-D Architectures for Semiconductor Integration and Packaging conference is scheduled for November 17 – 19, 2008 at the Hyatt Regency San Francisco Airport Hotel in Burlingame, CA. Organized by the Research Triangle Institute (RTI International) as part of its Technology Venture Forum Series, the conference brings together senior technologists and managers from leading companies, universities and research organizations involved in the 3D IC supply chain. For more information, visit: http://techventure.rti.org.
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