Ziptronix is currently a member of the following organizations:

CED
FSA
IMAPS
Semiconductor Research Corporation
3DIC Alliance

       
The Council for Entrepreneurial Development (CED)
CED was founded in 1984 to stimulate the creation and growth of high impact companies in the greater Research Triangle area. CED achieves its mission by providing programs and services in four major areas: education, capital formation, mentoring, and communications.  www.cednc.org

The Fabless Semiconductor Association (FSA)
FSA encourages the relationship between fabless companies and suppliers; facilitates business partnerships; creates awareness of and promotes the fabless business model; disseminates relevant data; and fosters standards and policies. www.fsa.org

International Microelectronics and Packaging Society (IMAPS)
IMAPS is the largest society dedicated to the advancement and growth of the use of microelectronics and electronic packaging through professional and public education, the dissemination of information (by symposia, conferences, workshops, and other efforts) and the promotion of the Society's portfolio of technologies.  www.imaps.org

Semiconductor Research Corporation
Semiconductor Research Corporation, arguably the world's premier research management consortium, directs a university-based program of basic and applied research. Member companies may exert influence on program direction and collaborate in the research process, while gaining early access to SRC's portfolio of research results and its pipeline of highly-trained PhD students. www.src.org

The 3D-IC Alliance (Ziptronix is a founding member)
The 3DIC Alliance is a consortium of integrated circuit designers, developers, and manufacturers. Its objective is to promote standards for three-dimensional integrated circuits (3D ICs) in order to accelerate their availability and acceptance. Industry-wide standards would allow virtually any semiconductor vendor to implement 3D technology.

The Alliance will publish specifications for ICs and/or wafers that are to be stacked and vertically integrated. Any ICs or wafers that are processed and designed to these standards should be 3D integratable by most (if not all) Alliance members. The Alliance may also work to produce specific protocols and signaling and electrical specifications to allow broad adoption and interchange between various die-level or wafer-level vendors.

The initial focus for the Alliance is standardization of the vertical interconnect requirements. These specifications will include a minimum set of global rules for pad sizing and spacing, interconnect keepout requirements, and material restrictions or requirements. The specifications should accommodate embedded interconnect systems as well as various methods for adding backside or frontside interconnect. www.3d-ic.org